Philips Manuals (Industrial)

The 74F574 is functionally identical to the 74F374 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocesors.

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The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates.

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The LVT652 is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device combines low static and dynamic power dissipation with high speed and high output drive. The 74LVT652 transceiver/register consists of bus transceiver circuits with 3-State outputs, D

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The 74ALVT162821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. It is designed for VCC operation at 2.5V or 3.3V with I/O compatibility to 5V. The 74ALVT162821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates.

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The 74ALVCH16841 has two 10-bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE) and output enable (nOE) control gates.

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The 74ALVT16652 is a high-performance BiCMOS product designed for VCC operation at 2.5V or 3.3V with I/O compatibility up to 5V. The device can be used as two 8-bit transceivers or one 16-bit transceiver.

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The LVT640 is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device is an octal transceiver featuring inverting 3-State bus compatible outputs in both send and receive directions. The control function implementation minimizes external timing requirements. The device features an Output Enable (OE) input for easy cascading and a Direction (DIR) input for direction control.

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The 74LVT16240A is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an inverting 16-bit buffer that is ideal for driving bus lines. The device features four Output Enables (1OE, 2OE, 3OE, 4OE), each controlling four of the 3-State outputs.

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The 74ALVCH162245 is a 16-bit transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. The 74ALVCH162245 features two output enable (nOE) inputs for easy cascading and two send/receive (nDIR) inputs for direction control. nOE controls the outputs so that the buses are effectively isolated. This device can be used as two 8-bit transceivers or one 16-bit transceiver.

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The 74F244 is an octal buffer that is ideal for driving bus lines of buffer memory address registers. The outputs are all capable of sinking 64mA and sourcing up to 15mA, producing very good capacitive drive characteristics. The device features two output enables, OEa and OEb, each controlling four of the 3-State outputs. The 74F244B is functionally equivalent to the 74F244. It has been designed to reduce effects of ground noise. Other advantages are noted in the features.

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The 74ALVC16835A is a 18

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The 74ABT16373B high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT16373B device is a dual octal transparent latch coupled to two sets of eight 3-State output buffers. The two sections of the device are controlled independently by Enable (nE) and Output Enable (nOE) control gates.

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The 74ABT162245A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed. The 74ABT162245A device is a 16-bit transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. The control function implementation minimizes external timing requirements. The device features two Output Enable (1OE, 2OE) inputs for easy cascading and two Direction (1DIR, 2DIR) inputs for direction control.

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The 74ABT16374B high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT16374B has two 8-bit, edge triggered registers, with each register coupled to eight 3-State output buffers. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates.

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The 74ALVCH16646 consists of 16 non-inverting bus transceiver circuits with 3-State outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the

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The 74ALVC16834A is an 18-bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop.

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The 74ALVC16836A is a 20-bit universal bus driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP).

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The 74ABT16827A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT16827A 20-bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. They have NOR Output Enables (nOE1, nOE2) for maximum control flexibility

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The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stor

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The 74ALVC162834A is an 18-bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop. The 74ALVC162834A is designed with 30
_series resistors in both HIGH or LOW output stages.

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