intersil 82C37A handbook

Update: 30 September, 2023

This data sheet provides a detailed description of the features and characteristics of the 82C37A CMOS high performance programmable DMA controller. The controller is compatible with the NMOS 8237A and features four independent maskable channels with autoinitial- ization capability. It is also cascadable to any number of channels and supports high speed data transfers of up to 4MBytes/sec with an 8MHz clock and up to 6.25MBytes/sec with a 12.5MHz clock. The controller also supports memory-to-memory transfers and is designed using a static CMOS process that allows for low power operation (ICCSB = 10µA maximum, ICCOP = 2mA/MHz maximum). The controller is fully compatible with TTL and CMOS and internal registers may be read from software.

---

Brand: intersil

File format: PDF

Size: 154 KB

MD5 Checksum: 468AA8215865269A0F1B5DCE8D728F3B

Publication date: 11 June, 2012

Downloads: -

PDF Link: intersil 82C37A handbook PDF