NATIONAL SEMICONDUCTOR - LM4308 Mobile Pixel Link Two (MPL-2) 18-bit CPU Display Interface Master/Slave handbook
Update: 28 September, 2023
The LM4308 device adapts a 18-bit CPU style display interfaces to a MPL-2 SLVS differential serial link for displays. Two chip selects support a main and sub display up to and beyond 640 x 480 pixels. A mode pin configures the device as a Master (MST) or Slave (SLV). Both WRITE and READ operations are supported. CPU interface widths below 18-bits are supported by tieing unused inputs to a static level. The differential line drivers and receivers conform to the JEDEC SLVS Standard. When noise is picked up as common-mode, it is rejected by the receivers. This is further enhanced with the 50 Ohm output impedance of the drivers. The 100 Ohm termination is integrated into the receivers. Data integrity is insured with a 5-bit CRC field. CRC checking is done for both WRITE and READ operations. An Error (ERR) pin reports the occurrence of an error. A Write Only mode is also provided. The interconnect is reduced from 23 signals to only 4 active signals with the LM4308 chipset easing flex interconnect design, size constraints and cost. A low power sleep state entered when the PD* inputs are driven low.
Brand: National
File format: PDF
Size: 1106 KB
MD5 Checksum: 4124E7F1CE84325DF3C07B39503BE3B9
Publication date: 04 May, 2012
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